Data processors typically perform in locked operand transfer sequences in which one operand transfer may be immediately followed by another transfer or transfers of operands. Previously, during such locked operand transfer sequences a data processor will not allow a system communication bus to be taken away from it before the locked operand transfer sequence is completed. An example of an instruction which may require a locked operand transfer sequence is `compare and swap` instruction where a received operand is compared by a data processor with a previously stored operand and if the values differ, the received operand is exchanged with the previously stored operand. Also, an instruction sequence during which a `read` of an operand, a `modify` of the operand and a `write` of the operand are performed is another operand transfer sequence in which no interruption is desired. If a locked sequence is broken, an error typically results. Therefore, the sequence of operations requires a locking mechanism in a complex data processing system to prevent other processors from interfering with the sequence and affecting the validity of the data processing operation before the operation is completed. However, there may be a plurality of consecutive locked operand transfer sequences which may allow one processor to monopolize use of a common system communication bus to the exclusion of all other processors coupled to the communication bus. A real need in the system may exist to break the locking mechanism in order to allow a higher priority processor access to the bus.
Communication bus arbiter circuits are commonly used to control which one of a plurality of processors is allowed to have bus mastership and control of the system's communication bus. However, in synchronous bus systems where data is always communicated at a synchronous clock rate, bus arbiters are often unable to determine a satisfactory point in time at which bus ownership may be safely taken away from an existing bus master when a plurality of successive locked transfer sequences is executed. As a result, bus arbiters typically do not allow transfer of bus mastership until the present bus master has finished all locked operand transfer sequences and the current bus master indicates a completion of the locked sequences thereby allowing interruption of bus mastership by the arbiter. Therefore, a processor requiring bus mastership may be prevented from using the system communication bus for a long period of time even though the bus arbiter recognizes that the requesting processor has a higher system priority.